The synchronization problem
Serial communication normally consists of transmitting binary data across an electrical or optical link such asor V.35. The data, being binary, is usually represented by two physical states. For example, +5v may represent 1 and -5v represent 0. The accurate decoding of the data at the remote end is dependent on the sender and receiver maintaining synchronization during decoding. The receiver must sample the signal in phase with the sender.
If the sender and receiver were both supplied by exactly the same clock source, then transmission could take place forever with the assurance that signal sampling at the receiver was always in perfect synchronization with the transmitter. This is seldom the case, so in practice the receiver is periodically brought into synch. with the transmitter. It is left to the internal clocking accuracy of the transmitter and receiver to maintain sampling integrity between synchronization pulses.
This is the method most widely used for PC or simple terminal serial communications.
In asynch. serial communication, the electrical interface is held in the mark position between characters. The start of transmission of a character is signaled by a drop in signal level to the space level. At this point, the receiver starts its clock. After one bit time (the start bit) come 8 bits of true data followed by one or more stop bits at the mark level. The receiver tries to sample the signal in the middle of each bit time. The byte will be read correctly if the line is still in the intended state when the last stop bit is read.
Thus the transmitter and receiver only have to have approximately the same clock rate. A little arithmetic will show that for a 10 bit sequence, the last bit will be interpreted correctly even if the sender and receiver clocks differ by as much as 5%.
Asynchronous is relatively simple, and therefore inexpensive. However, it has a high overhead, in that each byte carries at least two extra bits: a 25% loss of line bandwidth. A 56kbps line can only carry 5600 bytes/second asynchronously, in ideal conditions.
In synchronous communications, data is not sent in individual bytes, but as frames of large data blocks. Frame sizes vary from a few bytes through 1500 bytes for Ethernet or 4096 bytes for mostsystems. The clock is embedded in the data stream encoding, or provided on separate clock lines such that the sender and receiver are always in synchronization during a frame transmission. Most modern framing is built on the High-Level Data Link Control (HDLC) frame structure. An HDLC frame has the following general structure:
|FLAG||ADDRESS||CONTROL||DATA PAYLOAD||CRC BYTES||FLAG|
The flag is a sequence 01111110 which delimits the start of the frame. A technique known as bit stuffing is used to insert additional zeros into the data so that a flag sequence never appears anywhere but at the start and end of a frame. These extra bits are “unstuffed” again by the receiver.
The address field is usually one byte, but may be more. It is used to indicate the sender or intended receiver of the frame. It is possible to have multiple stations connected to a single wire, and to design the system so that each receiver only “sees” frames with its own address. By this means multiple stations can communicate with each other using just one line (for instance on a Local Area Network).
The control field is one or more bytes. It contains information on the type of frame (for instance, whether this is a frame containing user data or a supervisory frame which performs some sort of link control function). It also often contains a rotating sequence number that allows the receiver to check that no frame has been lost.
The “payload” of the frame is the data field. The data in this field is completely transparent. In fact, it does not even have to be organized in 8 bit bytes, it is a purely arbitrary collection of bits.
Following the data field are two bytes comprising the Cyclic Redundancy Check(CRC). The value of these bytes is the result of an arithmetic calculation based on every bit of data between the flags. When the frame is received, the calculation is repeated and compared with the received CRC bytes. If the answers match then we are sure to a very high degree of certainty that the frame has been received exactly as transmitted. If there is a CRC error the received frame is usually discarded.
Finally, the frame is terminated by another flag character.
Synchronous communication is usually much more efficient in use of bandwidth than Asynch. The data field is usually large in comparison to the flag, control, address, and CRC fields, so there is very little overhead. A 56kbps synchronous line can be expected to carry close to 7000 bytes per second (i.e. 56000/8, whereas the asynch. data rate would be 56000/10). Another advantage of synchronous communications is that the frame structure allows for easy handling of control information. There is a natural position (usually at the start of the frame) for any special codes that are needed by the communication protocol.
The HDLC framing.supported by Sangoma communications objects are nearly all synchronous, and most are based on